The present invention relates to a semiconductor memory device of a high packing density, such as a dynamic random-access memory (hereinafter referred to as DRAM), and in particular to a precharge and equalization circuit for quickly bringing a pair of data lines to a fixed potential.
An example of conventional equalizing circuit is shown U.S. Pat. No. 5,036,492. The equalizing circuit is formed of two transistors provided between a pair of bit lines connected to a precharge circuit for supplying a predetermined potential. The two transistors have their sources connected respectively to the data lines, their drains connected with each other, and their gates to which complementary equalizing signals are supplied. A bleeder current device is also connected to the drains. With such a configuration, the two transistors are concurrently activated, by means of the complementary equalizing signals, to set the bit lines at a same potential. The bleeder current device absorbs or supplies current so that the potentials on the bit lines do not depart from the set potential.
The above-described equalizing circuit requires a precharge circuit, and two control signals are required to control the precharge circuit and the equalizing circuit, so that the control over operation is complicated, and it is difficult to increase the overall operation speed of the device.